Semiconductor device

ABSTRACT

A semiconductor device includes a lower electrode structure, an upper electrode structure, and a dielectric layer between the lower and upper electrode structures and on side surfaces and an upper surface of the lower electrode structure. The lower electrode structure includes a first lower electrode pattern having a cylindrical shape, a barrier layer on the first lower electrode pattern, and a second lower electrode pattern in a space defined by the barrier layer.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2016-0088706, filed on Jul. 13, 2016, and entitled, “Semiconductor Device,” is incorporated by reference herein in its entirety.

BACKGROUND 1. Field

One or more embodiments described herein relate to a semiconductor device.

2. Description of the Related Art

Various types of semiconductor memory devices have been developed. One example is a dynamic random access memory (DRAM). Attempts have been made to increase the integration of DRAMs. However, these attempts have reduced the memory cell area and/or have produced other drawbacks.

SUMMARY

In accordance with one or more embodiments, a semiconductor device includes a substrate, a lower electrode structure above the substrate and extending in a direction crossing an upper surface of the substrate, a dielectric layer on side surfaces and an upper surface of the lower electrode structure, and an upper electrode structure on the dielectric layer, wherein the lower electrode structure includes a first lower electrode pattern having a cylindrical shape, a barrier layer on the first lower electrode pattern, and a second lower electrode pattern in a space defined by the barrier layer.

In accordance with one or more other embodiments, a semiconductor device includes a substrate, contact plugs in an interlayer insulation pattern layer on the substrate, lower electrode structures above the substrate, abutting respective ones of the contact plugs, and extending in a direction crossing an upper surface of the substrate, supports connecting adjacent lower electrode structures, from among the lower electrode structures, to each other, a dielectric layer along external surfaces of the lower electrode structures and the supports, and an upper electrode structure on the dielectric layer, wherein each of the lower electrode structures includes a first lower electrode pattern having a cylindrical shape, a barrier layer on the first lower electrode pattern, and a second lower electrode pattern in a space defined by the barrier layer.

In accordance with one or more other embodiments, a capacitor includes a lower and upper electrode structures and a dielectric layer between the lower and upper electrode structures, wherein the lower electrode structure includes a first electrode pattern, a second electrode pattern, and a barrier layer, the barrier layer on the first electrode pattern and the second electrode pattern in a space defined by the barrier layer.

BRIEF DESCRIPTION OF THE DRAWINGS

Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which:

FIG. 1A illustrates an embodiment of a semiconductor device, and FIG. 1B illustrates a view along section line A-A′ in FIG. 1A;

FIG. 2 illustrates an example of a rate of increase in resistance based on the width of a lower electrode before and after a dielectric layer formation process;

FIG. 3 illustrates examples of a rate of increase in resistance based on a lower electrode structure before and after a dielectric layer formation process;

FIG. 4A illustrates examples of a proportion of semiconductor devices based on a number of bridge fail bits, and FIG. 4B illustrates an example of a proportion of semiconductor devices based on a number of resistive fail bits;

FIG. 5A illustrates examples of a proportion of semiconductor devices based on a number of bridge fail bits in ones that have different widths of second lower electrode patterns, and FIG. 5B illustrates examples of a proportion of semiconductor devices based on a number of resistive fail bits;

FIG. 6 illustrates another embodiment of a semiconductor device;

FIG. 7 illustrates another embodiment of a semiconductor device;

FIG. 8A illustrates a cross-sectional view of an embodiment of a semiconductor device, and FIG. 8B illustrates an enlarged view of part M in FIG. 8A;

FIG. 9A illustrates a cross-sectional view an embodiment of a semiconductor device, and FIG. 9B illustrates a view along section line B-B′ in FIG. 9A;

FIG. 10 illustrates another embodiment of a semiconductor device;

FIGS. 11A-11F illustrate various stages in an embodiment of a method for manufacturing the semiconductor device in FIGS. 1A and 1B;

FIG. 12 illustrates various stages in an embodiment of a method for manufacturing the semiconductor device in FIGS. 9A and 9B; and

FIGS. 13A-13D illustrate various stages in an embodiment of a method for manufacturing the semiconductor device in FIG. 10.

DETAILED DESCRIPTION

FIG. 1A is a cross-sectional view an embodiment of a semiconductor device 100, and FIG. 1B is a cross-sectional view taken along line A-A′ in FIG. 1A Referring to FIGS. 1A and 1B, the semiconductor device 100 may include a substrate 101, a lower electrode structure 119 above the substrate 101, a dielectric layer 121 on side surfaces and an upper surface of the lower electrode structure 119, and an upper electrode structure 123 on the dielectric layer 121. The lower electrode structure 119 may include a first lower electrode pattern 113 a having a predetermined (e.g., cylinder) shape, a barrier layer 115 a on the first lower electrode pattern 113 a, and a second lower electrode pattern 117 a in a space defined by the barrier layer 115 a. Electrode pattern 113 a may have a different shape in another embodiment.

The barrier layer 115 a may prevent the occurrence of a bridge between adjacent lower electrode structures 119 and an increase in node resistance of the lower electrode structure 119, by suppressing excessive oxidation of the lower electrode structure 119 during a process of forming the dielectric layer 121.

An interlayer insulation layer 103 may be on the substrate 101, and a contact plug 105 may penetrate the interlayer insulation layer 103 and may be electrically connected to the substrate 101. The substrate 101 may be a semiconductor substrate, for example, a substrate including one or more semiconductor materials of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, or InP, a silicon-on-insulator (SOI) substrate, or the like. The substrate 101 may further include a transistor and/or lines. The contact plug 105 may be connected to the transistor and/or the lines of the substrate 101. The contact plug 105 may include, for example, doped polysilicon or a metal material.

An etch stop layer 107 may be on the interlayer insulation layer 103 and may have a shape and/or structure which selectively exposes an upper surface of the contact plug 105.

The lower electrode structure 119 may abut the upper surface of the contact plug 105 and extend in a direction (direction Z) perpendicular to an upper surface of the substrate 101. The lower electrode structure 119 may include the first lower electrode pattern 113 a having a predetermined (e.g., cylindrical) shape, the barrier layer 115 a on the first lower electrode pattern 113 a, and the second lower electrode pattern 117 a in a space defined by the barrier layer 115 a. The thickness T1 of the first lower electrode pattern 113 a may be less than a width W of the second lower electrode pattern 117 a. The thickness T2 of the barrier layer 115 a may be less than the width W of the second lower electrode pattern 117 a. In one example, the thickness T1 of the first lower electrode pattern 113 a may be about 1 to about 30 Å, the thickness T2 of the barrier layer 115 a may be about 1 to about 30 Å, and the width W of the second lower electrode pattern 117 a may be about 10 to about 300 Å.

The barrier layer 115 a may block O₃, which is a reaction gas of the formation process of the dielectric layer 121. As a result, O₃ may not intrude into the second lower electrode pattern 117 a. Accordingly, a region of the second lower electrode pattern 117 a that is oxidized by the reaction gas O₃ may be decreased. Thus, node resistance increase or a bridge phenomenon between adjacent lower electrode structures caused by volume expansion may be suppressed. At the same time, the first lower electrode pattern 113 a thinly formed on the barrier layer 115 a may provide a base to allow for deposition of the dielectric layer 121. For example, because crystallinity, adhesiveness, and the like, of the dielectric layer 121 are determined according to a lower layer of the dielectric layer 121, the dielectric layer 121 with excellent properties may be formed by providing the first lower electrode pattern 113 a having metallicity as the lower layer of dielectric layer 121.

Even in this case, the first lower electrode pattern 113 a may be partially oxidized by the reaction gas O₃. However, since the thickness T1 of the first lower electrode pattern 113 a is less than the width W of the second lower electrode pattern 117 a, an increase in the overall resistance of the lower electrode structure 119 and the bridge phenomenon caused by volume expansion may be suppressed.

The barrier layer 115 a may be metal silicon nitride. For example, the barrier layer 115 a may be TiSiN, TaSiN, WSiN, ZrSiN, AlSiN, or the like. In some embodiments, the barrier layer 115 a may have a silicon concentration gradient in a thickness direction of the barrier layer 115 a. For example, the concentration of silicon in the barrier layer 115 a may decrease in a direction from a first interface between the first lower electrode pattern 113 a and the barrier layer 115 a to a second interface between the barrier layer 115 a and the second lower electrode pattern 117 a.

In some embodiments, the barrier layer 115 a may have a multilayer structure in which a silicon concentration of an upper barrier layer may be lower than that of a lower barrier layer. In some embodiments, the barrier layer 115 a may have a structure including a metal nitride layer and a silicon nitride layer which are stacked alternately at least once.

The first and second lower electrode patterns 113 a and 117 a include metal or metal nitride. For example, each of the first and second lower electrode patterns 113 a and 117 a may include at least one of Ti, TiN, W, WN, Ta, TaN, HfN, ZrN, TiAlN, TaSiN, TiSiN, TaAlN, or the like. Each of the first and second lower electrode patterns 113 a and 117 a may have a single-layer structure or a multilayer structure.

The dielectric layer 121 may be on the side surfaces and the upper surface of the lower electrode structure 119. A top surface 113 aT of the first lower electrode pattern 113 a, a top surface 115 aT of the barrier layer 115 a, and a top surface 117 aT of the second lower electrode pattern 117 a may be at the same level as one another. The dielectric layer 121 may cover the top surface 113 aT of the first lower electrode pattern 113 a, the top surface 115 aT of the barrier layer 115 a, and the top surface 117 aT of the second lower electrode pattern 117 a. In some embodiments, the second lower electrode pattern 117 a may cover the top surface 113 aT of the first lower electrode pattern 113 a and the top surface 115 aT of the barrier layer 115 a.

The dielectric layer 121 may have a single layer structure including a tantalum oxide film (Ta₂O₅), an aluminum oxide film (Al₂O₃), or a titanium oxide film (TiO) or may have a multilayer structure including tantalum oxide film/titanium oxide film, aluminum oxide film/titanium oxide film, or the like.

The upper electrode structure 123 may be on the dielectric layer 121. The upper electrode structure 123 may include metal or metal nitride. For example, the upper electrode structure 123 may include at least one of Ti, TiN, W, WN, Ta, TaN, HfN, ZrN, TiAlN, TaSiN, TiSiN, TaAlN, or the like. The upper electrode structure 123 may have a single-layer structure or a multilayer structure.

FIG. 2 is a graph showing an example a rate of increase in resistance based on the width of a lower electrode of a proposed semiconductor device before and after a dielectric layer formation process. FIG. 3 is a graph showing examples of rates of increase in sheet resistance according to the lower electrode structures of comparative examples and an embodiment before and after a dielectric layer formation process.

When the resistance of the lower electrode of a capacitor increases, node resistance of the capacitor increases. Thus, performance of a semiconductor device may degrade. A reaction gas introduced during a dielectric layer formation process may oxidize the lower electrode and increase the resistance of the lower electrode.

In FIG. 2, trend line 1 L1 corresponds to resistance based on the width of a lower electrode before a dielectric layer formation process. Trend line 2 L2 corresponds to resistance based on the width of a lower electrode after the dielectric layer formation process. Trend line 3 L3 corresponds to the rate of increase in resistance based on the width of a lower electrode before and after the dielectric layer formation process.

Referring to the trend line 1 L1, resistance increases as the width of the lower electrode decreases. Accordingly, as the semiconductor device tends to be integrated, a resistance increase of the lower electrode is unavoidable and a structure for suppressing additional resistance increase is necessary.

Referring to the trend line 2 L2, after the process of forming a dielectric layer on the lower electrode, resistance increases in every width range of the lower electrode. Also, the width of resistance increase greatly increases as the width of the lower electrode decreases.

Referring to the trend line 3 L3, the rate of increase in resistance before and after the dielectric layer formation process increases as the width of the lower electrode decreases. When the width of the lower electrode is about 7.5, the rate of increase in resistance after the dielectric layer formation process is about 17.9%. When the width of the lower electrode is about 3, the rate of increase in resistance after the dielectric layer formation process increases to about 124.6%. Thus, as the width of the lower electrode tends to decrease, oxidation of the lower electrode caused by the dielectric layer formation process may affect resistance of the lower electrode more significantly.

Referring to FIG. 3, comparative example 1 corresponds to a lower electrode including a metal material, and more particularly, TiN. Comparative example 2 corresponds to a lower electrode including a barrier layer material, and more particularly, TiSiN. The example embodiment corresponds to a lower electrode structure in FIGS. 1A and 1B, namely, a lower electrode structure including a first lower electrode pattern including TiN, a barrier layer including TiSiN on the first lower electrode pattern, and a second lower electrode pattern including TiN on the barrier layer. The thickness of the first lower electrode pattern may be less than the width of the second lower electrode pattern.

Referring to comparative example 1, the sheet resistance of the lower electrode before a dielectric layer formation process is about 0.70, and the sheet resistance of the lower electrode after the dielectric layer formation process increases to about 1.38. Thus, the rate of increase in sheet resistance is about 97%. Thus, the lower electrode is oxidized by a reaction gas O₃ introduced during the dielectric layer formation process. Thus, sheet resistance of the lower electrode may greatly increase. In this case, the sheet resistance far exceeds a resistance level that is planned in semiconductor device design, and thus reliability of a semiconductor device may degrade.

Referring to comparative example 2, the sheet resistance of the lower electrode before a dielectric layer formation process is about 6.00, and the sheet resistance of the lower electrode after the dielectric layer formation process is about 7.50. Thus, sheet resistance of the material itself is very high. Accordingly, apart from the rate of increase in sheet resistance caused by the dielectric layer formation process, the lower electrode corresponding to comparative example 2 may be hard to use in a semiconductor device requiring low-resistive node resistance.

Referring to the example embodiment, the sheet resistance of the lower electrode before a dielectric layer formation process is about 0.60, and the sheet resistance of the lower electrode after the dielectric layer formation process increases to about 0.66. Thus, the rate of increase in sheet resistance is about 10%. As a result, the resistance level planned in semiconductor device design may be relatively stably maintained, and reliability of a semiconductor device may be therefore be obtained.

Moreover, a reaction gas O₃ introduced during the dielectric layer formation process of the example embodiment may mainly react with the first lower electrode pattern corresponding to a surface of the lower electrode structure, and intrusion of the reaction gas O₃ into the second lower electrode pattern may be suppressed by the barrier layer. Accordingly, oxidization of the second lower electrode pattern occupying most of the lower electrode structure is suppressed. Thus, the rate of increase in overall sheet resistance of the lower electrode structure may be very low.

Referring to FIGS. 1A and 1B, in some embodiments, a first sheet resistance of the first lower electrode pattern 113 a may be about twice as much as a second sheet resistance of the second lower electrode pattern 117 a or greater. The first sheet resistance of the first lower electrode pattern 113 a may correspond to about 1.38, which is the sheet resistance of the lower electrode after the dielectric layer formation process in comparative example 1. The second sheet resistance of the second lower electrode pattern 117 a may correspond to a numerical value less than about 0.66, which is the sheet resistance of the lower electrode after the dielectric layer formation process in the embodiment.

According to the graph of FIG. 3, the first sheet resistance of the first lower electrode pattern 113 a may be about 2.1 times greater than the second sheet resistance of the second lower electrode pattern 117 a. The difference in sheet resistance between the first lower electrode pattern 113 a and the second lower electrode pattern 117 a may be generated by oxidation caused by the reaction gas O₃. Since the second lower electrode pattern 117 a has the reaction gas O₃ blocked by the barrier layer 115 a, and thus oxidation of the second lower electrode pattern 117 a is suppressed, the second lower electrode pattern 117 a may have a sheet resistance less than that of the first lower electrode pattern 113 a.

FIG. 4A is a graph showing proportions of memory chips based on numbers of bridge fail bits in memory chips for comparative example of a semiconductor device and an example embodiment of the semiconductor device 100 in FIGS. 1A and 1B. FIG. 4B is a graph showing proportions of memory chips based on numbers of resistive fail bits for the comparative example and the example embodiment.

Referring to FIG. 4A, in the example embodiment, about 80% of the total memory chips have bridge fail bits in a first fail bit number N1 or less. On the other hand, in the comparative example, the proportion of memory chips having bridge fail bits in the first fail bit number N1 or less in the total memory chips is merely about 30%. In the comparative example, about 80% of the total memory chips is in a range equal to or less than a second fail bit number N2, which corresponds to about twice the first fail bit number N1. Thus, in a semiconductor device including a lower electrode structure corresponding to the example embodiment, a bridge phenomenon between lower electrode structures is suppressed and the frequency of occurrence of bridge fail bits is low. Thus, a memory chip having high reliability may be provided.

Referring to FIG. 4B, in the example embodiment, about 80% of the total memory chips have resistive fail bits in a first fail bit number N3 or less. On the other hand, in the comparative example, the proportion of memory chips having resistive fail bits in the first fail bit number N3 or less in the total memory chips is merely about 20% or about 40%. In the comparative example, about 80% of the total memory chips is in a range equal to or less than a second fail bit number N4, which is about quadruple the first fail bit number N3. Thus, in a semiconductor device including a lower electrode structure corresponding to the example embodiment, the increase in resistance of the lower electrode structure is suppressed and the frequency of occurrence of resistive fail bits is low. Thus, a memory chip having high reliability may be provided.

FIG. 5A is a graph showing proportions of memory chips based on numbers of bridge fail bits in memory chips for different embodiments of the semiconductor device 100 in FIGS. 1A and 1B. FIG. 5B is a graph showing proportions of memory chips based on numbers of resistive fail bits for different embodiments. In FIGS. 5A and 5B, embodiment 1 may be memory chips including semiconductor devices having second lower electrode patterns that are about 40 Å in width, and embodiment 2 may be memory chips including semiconductor devices having second lower electrode patterns that are about 20 Å in width.

Referring to FIG. 5A, in embodiment 1, the total memory chips have bridge fail bits in a first fail bit number N5 or less. In embodiment 2, the proportion of memory chips having bridge fail bits in the first fail bit number N5 or less in the total memory chips is merely about 10% or less. In embodiment 2, about 40% or about 70% of the total memory chips is in a range equal to or less than a second fail bit number N6, which is about quintuple the first fail bit number N5. Thus, in the lower electrode structure 119 in the semiconductor device 100 of FIGS. 1A and 1B, when the width W of the second lower electrode pattern 117 a is about 40 Å or greater, a bridge phenomenon between lower electrode structures 119 may be suppressed and the frequency of occurrence of bridge fail bits is low. Thus, a memory chip with high reliability may be provided.

Referring to FIG. 5B, in embodiment 1, 80% of the total memory chips has resistive fail bits in a first fail bit number N7 or less. In embodiment 2, the proportion of memory chips having resistive fail bits in the first fail bit number N7 or less in the total memory chips is merely about 20%. In embodiment 2, about 80% of the total memory chips is in a range equal to or less than a second fail bit number N8, which is about sextuple the first fail bit number N7. Thus, in the lower electrode structure 119 in the semiconductor device 100 of FIGS. 1A and 1B, when the width W of the second lower electrode pattern 117 a is about 40 Å or greater, the increase in resistance of the lower electrode structure 119 is suppressed. Accordingly, the frequency of occurrence of resistive fail bits is low. Thus, a memory chip having high reliability may be provided.

FIG. 6 is a cross-sectional view of another embodiment of a semiconductor device 200. The semiconductor device 200 is similar to the semiconductor device 100 in FIGS. 1A and 1B, except for a silicon concentration gradient in a barrier layer 215 a.

Referring to FIG. 6, the semiconductor device 200 may include the substrate 101, a lower electrode structure 219 above the substrate 101, the dielectric layer 121 on side surfaces and an upper surface of the lower electrode structure 219, and the upper electrode structure 123 on the dielectric layer 121. The lower electrode structure 219 may include the first lower electrode pattern 113 a having a predetermined (e.g., cylindrical) shape, the barrier layer 215 a on the first lower electrode pattern 113 a, and the second lower electrode pattern 117 a in a space defined by the barrier layer 215 a.

The barrier layer 215 a may have a silicon concentration gradient in which the concentration of silicon in the barrier layer 215 a decreases in a direction from a first interface INF1 between the first lower electrode pattern 113 a and the barrier layer 215 a to a second interface INF2 between the barrier layer 215 a and the second lower electrode pattern 117 a. A region of the barrier layer 215 a that abuts the first interface INF1 has a high silicon concentration, and thus may defend against intrusion of a reaction gas O₃ introduced for a dielectric layer formation process. At the same time, a region of the barrier layer 215 a that abuts the second interface INF2 has a low silicon concentration, and thus may control resistance of the lower electrode structure 219 itself not to be increased by the barrier layer 215 a.

In some embodiments, the barrier layer 215 a may be metal silicon nitride having a silicon concentration gradient in a thickness direction of the barrier layer 215 a. For example, the barrier layer 215 a may be TiSiN, TaSiN, WSiN, ZrSiN, AlSiN, or the like, having a silicon concentration gradient in a thickness direction of the barrier layer 215 a. The silicon concentration gradient may be formed, for example, by adjusting flow of a silicon source for forming the barrier layer 215 a. For example, the silicon concentration gradient may be formed by increasing flow of SiH₄ or SiH₂Cl₂, which is a silicon source, during an early period of forming the barrier layer 215 a on the first lower electrode pattern 113 a and gradually decreasing the flow of the silicon source according to time.

FIG. 7 is a cross-sectional view of another embodiment of a semiconductor device 300. The semiconductor device 300 is similar to the semiconductor device 100 of FIGS. 1A and 1B, except for a barrier layer 315 a which has a multilayer structure.

Referring to FIG. 7, the semiconductor device 300 may include the substrate 01, a lower electrode structure 319 above the substrate 101, the dielectric layer 121 on side surfaces and an upper surface of the lower electrode structure 319, and the upper electrode structure 123 on the dielectric layer 121. The lower electrode structure 319 may include the first lower electrode pattern 113 a having a predetermined (e.g., cylindrical) shape, the barrier layer 315 a on the first lower electrode pattern 113 a, and the second lower electrode pattern 117 a in a space defined by the barrier layer 315 a.

The barrier layer 315 a may include a structure in which a lower barrier layer 315 a 1 and an upper barrier layer 315 a 2 are stacked in the stated order. The lower barrier layer 315 a 1 may include metal silicon nitride having a first silicon concentration. The upper barrier layer 315 a 2 may include metal silicon nitride having a second silicon concentration lower than the first silicon concentration. The lower barrier layer 315 a 1 of the barrier layer 315 a, which abuts the first interface INF1, has the first silicon concentration that is high and, thus, may effectively defend against intrusion of a reaction gas O₃ introduced for a dielectric layer formation process. At the same time, the upper barrier layer 315 a 2 of the barrier layer 315 a, which abuts the second interface INF2, has the second silicon concentration that is low and, thus, may control resistance of the lower electrode structure 319 itself not to be increased by the barrier layer 315 a.

Each of the lower barrier layer 315 a 1 and the upper barrier layer 315 a 2 may include at least one of TaSiN, TaSiN, WSiN, ZrSiN, or AlSiN and, for example, may include different materials from each other.

FIG. 8A is a cross-sectional view of another embodiment of a semiconductor device 400. FIG. 8B is an enlarged view of part M in FIG. 8A. The semiconductor device 400 is similar to the semiconductor device 100 of FIGS. 1A and 1B, except that a barrier layer 415 a has a multilayer structure. For example, the barrier layer 415 a of the semiconductor device 400 may have a structure in which a layer including no silicon and a layer including silicon are alternately stacked at least once.

Referring to FIGS. 8A and 8B, the semiconductor device 400 may include the substrate 101, a lower electrode structure 419 above the substrate 101, the dielectric layer 121 on side surfaces and an upper surface of the lower electrode structure 419, and the upper electrode structure 123 on the dielectric layer 121. The lower electrode structure 419 may include the first lower electrode pattern 113 a having a predetermined (e.g., cylindrical) shape, the barrier layer 415 a on the first lower electrode pattern 113 a, and the second lower electrode pattern 117 a in a space defined by the barrier layer 415 a.

The barrier layer 415 a may have a multilayer structure in which a layer including no silicon and a layer including silicon are alternately stacked at least once. In some embodiments, the barrier layer 415 a may include a first metal nitride layer 415 a 1, a first silicon nitride layer 415 a 2, a second metal nitride layer 415 a 3, a second silicon nitride layer 415 a 4, and a third metal nitride layer 415 a 5 stacked on the first lower electrode pattern 113 a in the stated order. A first thickness T3 of the first metal nitride layer 415 a 1 may be less than a second thickness T4 of the second metal nitride layer 415 a 3. The second thickness T4 may be less than a third thickness T5 of the third metal nitride layer 415 a 5. A silicon concentration gradient in a thickness direction of the barrier layer 415 a may appear according to thickness differences in the first to third metal nitride layers 415 a 1, 415 a 3, and 415 a 5 adjacent to the first and second silicon nitride layers 415 a 2 and 415 a 4. For example, the silicon concentration gradient may increase in a direction toward the first lower electrode pattern 113 a of the barrier layer 415 a. Such a silicon concentration gradient may effectively defend against intrusion of a reaction gas O₃ introduced for a dielectric layer formation process.

In FIGS. 8A and 8B, the barrier layer 415 a includes five layers. In another embodiment, the barrier layer 415 a may include two to four or six or more layers.

FIG. 9A is a cross-sectional view of another embodiment of a semiconductor device 500 according to embodiments. FIG. 9B is a cross-sectional view taken along line B-B′ in FIG. 9A. The semiconductor device 500 is similar to the semiconductor device 100 of FIGS. 1A and 1B, except that a second lower electrode pattern 517 a is on a first lower electrode pattern 513 a and a barrier layer 515 a.

Referring to FIGS. 9A and 9B, the semiconductor device 500 may include the substrate 101, a lower electrode structure 519 above the substrate 101, the dielectric layer 121 on side surfaces and an upper surface of the lower electrode structure 519, and the upper electrode structure 123 on the dielectric layer 121. The lower electrode structure 519 may include the first lower electrode pattern 513 a having a predetermined (e.g., cylindrical) shape, the barrier layer 515 a on the first lower electrode pattern 513 a, and the second lower electrode pattern 517 a.

In one embodiment, the second lower electrode pattern 517 a may include a first portion 51701 filling a space defined by the barrier layer 515 a and a second portion 51702 covering a top surface 513 aT of the first lower electrode pattern 513 a and a top surface 515 aT of the barrier layer 515 a. Thus, a top surface 517 aT of the second lower electrode pattern 517 a may be at a higher level than the top surface 513 aT of the first lower electrode pattern 513 a and the top surface 515 aT of the barrier layer 515 a. Cross-sections of the first lower electrode pattern 513 a and the barrier layer 515 a may be U-shaped, and a cross-section of the second lower electrode pattern 517 a may be T-shaped. These cross-sectional shapes may be different in another embodiment.

The dielectric layer 121 covering the lower electrode structure 519 may abut side surfaces of the first lower electrode pattern 513 a and side surfaces and an upper surface of the second portion 517 aP2 of the second lower electrode pattern 517 a and may not abut the barrier layer 515 a.

Thus, in a cross-section of the lower electrode structure 519 taken long line B-B′, only cross-sections of the second lower electrode pattern 517 a, the dielectric layer 121, and the upper electrode structure 123 may be shown, and cross-sections of the first lower electrode pattern 513 a and the barrier layer 515 a may not be shown.

FIG. 10 is a cross-sectional view of another embodiment of a semiconductor device 600. The semiconductor device 600 is similar to the semiconductor device 100 of FIGS. 1A and 1B, except that supports 610-1 b and 610-2 b are between adjacent lower electrode structures 619, and a dielectric layer 621 and an upper electrode structure 623 extend along the lower electrode structures 619 and the supports 610-1 b and 610-2 b.

Referring to FIG. 10, the semiconductor device 600 may include the substrate 101, a plurality of lower electrode structures 619 above the substrate 101, the supports 610-1 b and 610-2 b connecting adjacent lower electrode structures 619 from among the plurality of lower electrode structures 619, the dielectric layer 621 extending along side surfaces and upper surfaces of the lower electrode structures 619 and the supports 610-1 b and 610-2 b, and the upper electrode structure 623 on the dielectric layer 621. Each of the lower electrode structures 619 may include a first lower electrode pattern 613 a having a predetermined (e.g., cylindrical) shape, a barrier layer 615 a on the first lower electrode pattern 613 a, and a second lower electrode pattern 617 a in a space defined by the barrier layer 615 a.

The supports 610-1 b and 610-2 b may each include an insulating material. For example, each of the supports 610-1 b and 610-2 b may include a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer. The supports 610-1 b and 610-2 b may prevent the lower electrode structures 619 from becoming slanted or falling down due to a high aspect ratio.

FIGS. 11A-11F illustrate various stages of an embodiment of a method for manufacturing the semiconductor device 100 in FIGS. 1A and 1B. Methods for manufacturing the semiconductor device 200 in FIG. 6, the semiconductor device 300 in FIG. 7, and the semiconductor device 400 in FIGS. 8A and 8B will also be described with reference to FIGS. 11A-11F.

Referring to FIG. 11A, a preliminary interlayer insulation layer may be formed on the substrate 101. The interlayer insulation layer 103, including a contact hole exposing a surface of the substrate 101, may be formed by etching a partial region of the preliminary interlayer insulation layer. The surface of the substrate 101 that is exposed to the bottom of the contact hole may be a surface of a transistor or a line in the substrate 101. The contact plug 105 may be formed by filling the contact hole with a conductive material and performing polishing to expose an upper surface of the interlayer insulation layer 103. The etch stop layer 107 may be formed on the interlayer insulation layer 103 and the contact plug 105, the etch stop layer 107 including an insulating material.

Referring to FIG. 11B, a mold layer 109 may be formed on the etch stop layer 107. The mold layer 109 may be a layer for forming the lower electrode structure 119 in FIGS. 1A and 1B. Accordingly, the thickness of the mold layer 109 may be formed to be the same as or higher than a height of the lower electrode structure 119. The mold layer 109 may include a material having high etch selectivity with respect to the etch stop layer 107. The mold layer 109 may include, for example, silicon oxide and may include BPSG, TOSZ, HDP, PE-TEOS, etc.

In FIG. 11B, the mold layer 109 has a single-layer structure. In another embodiment, mold layer 109 may have a multilayer structure of different materials. In some embodiments, instead of mold layer 109, a complex layer may be formed to include a sacrificial layer and a supporting layer alternately stacked at least once.

Referring to FIG. 11C, the mold layer 109 and the etch stop layer 107 of FIG. 11B may be partially etched to form an opening OP exposing an upper surface of the contact plug 105. Thus, an etch stop layer 107 and a mold layer pattern 109 a exposing the upper surface of the contact plug 105 may be formed on the interlayer insulation layer 103 and the contact plug 105.

Referring to FIG. 11D, a first lower electrode layer 113 covering inner side surfaces and the bottom of the opening OP of FIG. 11C may be formed. The first lower electrode layer 113 may be formed, for example, by atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD).

Afterwards, a preliminary barrier layer 115 may be formed on the first lower electrode layer 113. The preliminary barrier layer 115 may be formed by ALD, CVD, or PVD. The preliminary barrier layer 115 may be metal silicon nitride, for example, TiSiN, TaSiN, WSiN, ZrSiN, AlSiN, or the like. In some embodiments, when the preliminary barrier layer 115 is TiSiN, the preliminary barrier layer 115 may be formed by using SiH₄ or SiH₂Cl₂, which is a silicon source, TiCl₄, which is a titanium source, and N₂ or NH₃ gas, which is a nitrogen source.

Afterwards, a second lower electrode layer 117 may be formed on the preliminary barrier layer 115 to fill a space defined by the preliminary barrier layer 115. The second lower electrode layer 117 may be formed by ALD, CVD, or PVD.

Referring to FIG. 11E, upper portions of the first lower electrode layer 113, the preliminary barrier layer 115, and the second lower electrode layer 117 may be removed to expose an upper surface of the mold layer pattern 109 a. The removing process may be performed, for example, by a chemical mechanical polishing process or an etch back process. According to the removing process, the lower electrode structure 119 of FIGS. 1A and 1B may be formed to extend in a direction perpendicular to an upper surface of the substrate 101. The lower electrode structure 119 may include the first lower electrode pattern 113 a having a predetermined (e.g., cylindrical) shape, the barrier layer 115 a having a predetermined (e.g., cylindrical) shape in a space defined by the first lower electrode pattern 113 a, and the second lower electrode pattern 117 a having a predetermined (e.g., bar) shape in a space defined by the barrier layer 115 a.

Referring to FIG. 11F, the mold layer pattern 109 a may be removed from the substrate 101 and the lower electrode structure 119. The removing process of the mold layer pattern 109 a may be performed, for example, by a wet etching process. Side surfaces and an upper surface of the lower electrode structure 119 and an upper surface of the etch stop layer 107 may be exposed by the removing process of the mold layer pattern 109 a. Side surfaces and a top surface of the first lower electrode pattern 113 a, a top surface of the barrier layer 115 a, and a top surface of the second lower electrode pattern 117 a may be exposed by the removing process of the mold layer pattern 109 a.

After the removing process, the dielectric layer 121 covering the exposed side surfaces and upper surface of the lower electrode structure 119 may be formed. The dielectric layer 121 may include TiO₂ or TiON formed, for example, using TiH gas and O₃ gas as a reaction gas. The reaction gas O₃ may react with the first lower electrode pattern 113 a and oxidize the first lower electrode pattern 113 a. However, intrusion of the reaction gas O₃ into the second lower electrode pattern 117 a may be prevented by the barrier layer 115 a. Thus, oxidization of the second lower electrode pattern 117 a may be suppressed. The dielectric layer 121 may be formed by ALD, CVD, or PVD.

After the dielectric layer 121 is formed, a heat treatment process may be further performed. The heat treatment process may improve crystallinity of the first lower electrode pattern 113 a, that is a lower layer of the dielectric layer 121, and thus may improve crystallinity of the dielectric layer 121 formed on first lower electrode pattern 113 a. When crystallinity of the dielectric layer 121 increases, a dielectric constant of the dielectric layer 121 may increase.

Referring to FIGS. 1A and 1B, the upper electrode structure 123 may be formed on the dielectric layer 121 to manufacture the semiconductor device 100. The upper electrode structure 123 may be formed by ALD, CVD, or PVD.

A method for manufacturing the semiconductor device 200 of FIG. 6 may be in accordance with the process described with reference to FIGS. 11A to 11F, except that a silicon concentration gradient is formed in a thickness direction of preliminary barrier layer 115 during a formation process of preliminary barrier layer 115 in FIG. 11D.

Referring to FIG. 6, the barrier layer 215 a of FIG. 6 may be formed by adjusting flow of a silicon source according to process progress. For example, the silicon concentration gradient may be formed by increasing flow of SiH₄ or SiH₂Cl₂, which is a silicon source, during an early period of forming the barrier layer 215 a on the first lower electrode pattern 113 a and gradually decreasing the flow of the silicon source over time.

The methods for manufacturing the semiconductor devices 300 and 400 in FIGS. 7 to 8B may be in accordance with the process described with reference to FIGS. 11A-11F, except that a multilayer structure is formed during the formation process of the preliminary barrier layer 115 in FIG. 11D.

Referring to FIG. 7, the lower barrier layer 315 a 1 and the upper barrier layer 315 a 2 may be respectively formed using different materials as sources. Referring to FIGS. 8A and 8B, the first metal nitride layer 415 a 1, the first silicon nitride layer 415 a 2, the second metal nitride layer 415 a 3, the second silicon nitride layer 415 a 4, and the third metal nitride layer 415 a 5 may be stacked in this stated order on the first lower electrode pattern 113 a. The thicknesses T3, T4, and T5 of the first to third metal nitride layers 415 a 1, 415 a 3, and 415 a 5 may be different from one another, for example, based on different deposition time periods.

FIG. 12 illustrates various stages of an embodiment of a method for manufacturing the semiconductor device 500 in FIGS. 9A and 9B. The preceding process described with reference to FIGS. 11A to 11C may be applied the same to the method of manufacturing the semiconductor device 500.

Referring to FIG. 12, a preliminary first lower electrode layer and a preliminary barrier layer covering inner side surfaces and the bottom of the opening OP may be formed in the opening OP of the etch stop layer 107 and the mold layer pattern 109 a of FIG. 11C.

Afterwards, upper portions of the preliminary first lower electrode layer and the preliminary barrier layer may be removed to expose an upper surface of the mold layer pattern 109 a. The removing process may be performed, for example, by a chemical mechanical polishing process or an etch back process. The top surface 513 aT of the first lower electrode pattern 513 a and the top surface 515 aT of the barrier layer 515 a may be formed to be lower than a top surface 109T of the mold layer pattern 109 a.

Afterwards, referring to FIGS. 9A and 9B, the second lower electrode pattern 517 a filling the opening OP defined by the first lower electrode pattern 513 a and the barrier layer 515 a may be formed. The second lower electrode pattern 517 a may be formed to cover the top surface 513 aT of the first lower electrode pattern 513 a and the top surface 515 aT of the barrier layer 515 a. Succeeding processes described with reference to FIGS. 11E and 11F may be used to manufacture semiconductor device 500.

FIGS. 13A-13D illustrate various stages of an embodiment of a method for manufacturing the semiconductor device 600 in FIG. 10. The method for manufacturing the semiconductor device 600 is similar to the method described with reference to FIGS. 11A to 11F, except that sacrificial layers 609-1, 609-2, and 609-3 and supporting layers 610-1 and 610-2 are formed above the substrate 101 in order to form the supports 610-1 b and 610-2 b of FIG. 10.

Referring to FIG. 13A, the sacrificial layers 609-1, 609-2, and 609-3 and the supporting layers 610-1 and 610-2 may be alternately formed on the etch stop layer 107 that is formed on the interlayer insulation layer 103 and the contact plug 105. The sacrificial layers 609-1, 609-2, and 609-3 may include, for example silicon oxide. The sacrificial layers 609-1, 609-2, and 609-3 may include, for example, silicon nitride. In one embodiment, the sacrificial layers 609-1, 609-2, and 609-3 may include silicon nitride. In this case, the sacrificial layers 609-1 and 609-2 may include silicon oxide. The sacrificial layers 609-1, 609-2, and 609-3 may be formed to be thicker than the supporting layers 610-1 and 610-2.

Referring to FIG. 13B, the sacrificial layers 609-1, 609-2, and 609-3, the supporting layers 610-1 and 610-2, and the etch stop layer 107 may be partially etched to form openings exposing an upper surface of the contact plug 105. Thus, the etch stop layer 107, sacrificial patterns 609-1 a, 609-2 a, and 609-3 a, and supporting patterns 610-1 a and 610-2 a including the openings exposing the upper surface of the contact plug 105 may be formed on the interlayer insulation layer 103 and the contact plug 105.

Afterwards, preliminary first lower electrode layers and preliminary barrier layers covering inner side surfaces and the bottom of the openings may be formed, and preliminary second lower electrode layers filling spaces defined by the preliminary barrier layers may be formed.

Next, upper portions of the preliminary first lower electrode layers, the preliminary barrier layers, and the preliminary second lower electrode layers may be removed to expose an upper surface of the sacrificial pattern 609-3 a. According to the removing process, the lower electrode structures 619 extending in a direction perpendicular to an upper surface of the substrate 101 may be formed. The lower electrode structures 619 may each include the first lower electrode pattern 613 a, the barrier layer 615 a, and the second lower electrode pattern 617 a.

Referring to FIG. 13C, the sacrificial layers 609-1, 609-2, and 609-3 may be removed leaving the lower electrode structures 619 and the supporting patterns 610-1 a and 610-2 a. In this case, so that only supports 610-1 b and 610-2 b, from among the supporting patterns 610-1 a and 610-2 a, that connect at least two adjacent lower electrode structures 619 to each other may remain, the supporting patterns 610-1 a and 610-2 a excluding the supports 610-1 b and 610-2 b may be removed using a mask.

Referring to FIG. 13D, a process may be performed to form the dielectric layer 621 on exterior walls of the lower electrode structures 619 and to connect the supports 610-1 b and 610-2 b to the lower electrode structures 619. The dielectric layer 621 may be formed along side surfaces and upper surfaces of the lower electrode structures 619 and the supports 610-1 b and 610-2 b.

Afterwards, referring to FIG. 10, upper electrode structure 623 may be formed on the dielectric layer 621 of FIG. 13D to manufacture semiconductor device 600.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims. 

What is claimed is:
 1. A semiconductor device, comprising: a substrate; a lower electrode structure above the substrate and extending in a direction crossing an upper surface of the substrate; a dielectric layer on side surfaces and an upper surface of the lower electrode structure; and an upper electrode structure on the dielectric layer, wherein the lower electrode structure, the dielectric layer, and the upper electrode structure form a capacitor, and wherein the lower electrode structure includes: a first lower electrode pattern having a hollow shape; a barrier layer accommodated in the first lower electrode pattern; and a second lower electrode pattern in a space defined by the barrier layer, wherein a first sheet resistance of the first lower electrode pattern is equal to or greater than two times of a second sheet resistance of the second lower electrode pattern.
 2. The semiconductor device as claimed in claim 1, wherein: the first lower electrode pattern of the lower electrode structure entirely covers a bottom surface of the barrier layer of the lower electrode structure, and a width of the second lower electrode pattern is greater than a thickness of the first lower electrode pattern.
 3. The semiconductor device as claimed in claim 1, wherein the barrier layer includes metal silicon nitride.
 4. The semiconductor device as claimed in claim 3, wherein the barrier layer includes TiSiN.
 5. The semiconductor device as claimed in claim 3, wherein a silicon concentration in the barrier layer decreases in a direction from a first interface between the first lower electrode pattern and the barrier layer to a second interface between the barrier layer and the second lower electrode pattern.
 6. The semiconductor device as claimed in claim 3, wherein: the barrier layer has a multilayer structure including a lower barrier layer and an upper barrier layer that are stacked, and a silicon concentration of the upper barrier layer is less than that of the lower barrier layer.
 7. The semiconductor device as claimed in claim 1, wherein the barrier layer has a multilayer structure including a metal nitride layer and a silicon nitride layer are stacked alternately at least once.
 8. The semiconductor device as claimed in claim 7, wherein: the barrier layer includes a first metal nitride layer, a first silicon nitride layer, a second metal nitride layer, a second silicon nitride layer, and a third metal nitride layer stacked on the first lower electrode pattern in the stated order, a first thickness of the first metal nitride layer is less than a second thickness of the second metal nitride layer, and the second thickness is less than a third thickness of the third metal nitride layer.
 9. The semiconductor device as claimed in claim 1, wherein: a top surface of the first lower electrode pattern, a top surface of the barrier layer, and a top surface of the second lower electrode pattern are at a same level as one another, and the dielectric layer covers the top surface of the first lower electrode pattern, the top surface of the barrier layer, and the top surface of the second lower electrode pattern.
 10. The semiconductor device as claimed in claim 1, wherein the second lower electrode pattern includes: a first portion filling an internal space defined by the barrier layer; and a second portion covering a top surface of the first lower electrode pattern and a top surface of the barrier layer.
 11. The semiconductor device as claimed in claim 10, wherein: the first lower electrode pattern and the barrier layer have U-shaped cross-sections, and the second lower electrode pattern has a T-shaped cross-section.
 12. The semiconductor device as claimed in claim 10, wherein the dielectric layer abuts side surfaces of the first lower electrode pattern and side surfaces and a top surface of the second portion of the second lower electrode pattern and does not abut the barrier layer.
 13. The semiconductor device as claimed in claim 1, wherein a width of the second lower electrode pattern is about 40 Å or greater.
 14. A semiconductor device, comprising: a substrate; contact plugs in an interlayer insulation pattern layer on the substrate; lower electrode structures above the substrate, abutting respective ones of the contact plugs, and extending in a direction crossing an upper surface of the substrate; supports connecting adjacent lower electrode structures, from among the lower electrode structures, to each other; a dielectric layer along external surfaces of the lower electrode structures and the supports; and an upper electrode structure on the dielectric layer, wherein the lower electrode structures, the dielectric layer, and the upper electrode structure form a capacitor, and wherein each of the lower electrode structures includes: a first lower electrode pattern having a cylindrical shape; a barrier layer on the first lower electrode pattern; and a second lower electrode pattern in a space defined by the barrier layer.
 15. A capacitor, comprising: a lower electrode structure; an upper electrode structure; and a dielectric layer between the lower and upper electrode structures, wherein the lower electrode structure includes a first electrode pattern, a second electrode pattern, and a barrier layer, the barrier layer between the first electrode pattern and the second electrode pattern in a space defined by the barrier layer, wherein: the first electrode pattern of the lower electrode structure has a hollow shape, and accommodates the barrier layer and the second electrode pattern of the lower electrode structure therein, and wherein a first sheet resistance of the first electrode pattern of the lower electrode structure is equal to or greater than two times of a second sheet resistance of the second electrode pattern of the lower electrode structure.
 16. The capacitor as claimed in claim 15, wherein the first electrode pattern of the lower electrode structure entirely covers a bottom surface of the barrier layer of the lower electrode structure.
 17. The capacitor as claimed in claim 15, wherein the barrier layer includes metal silicon nitride.
 18. The capacitor as claimed in claim 15, wherein the first electrode pattern has a thickness less than a width of the second electrode pattern.
 19. The capacitor as claimed in claim 15, wherein: the barrier layer includes a silicon concentration that decreases from a first interface between the first electrode pattern and the barrier layer to a second interface between the barrier layer and the second electrode pattern. 